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 Posted: Wed Apr 11, 2012 4:00 pm Post subject: Apple TV A5 SoC is 32nm, Harvested dual-core A5 |
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The 3rd generation Apple TV ships with what Apple tells us is a single-core A5 SoC. After delayering the chip to the transistor gate layer in the new Apple TV, Chipworks just confirmed that the SoC is actually a 32nm dual-core part - presumably with one core disabled.</p>
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The iPhone 4S' A5 and the A5X used in the new iPad are both built on Samsung's 45nm LP process. This new A5 in the Apple TV is built on Samsung's 32nm High-K + Metal Gate (gate first) process. When transitioning to a new process node, it's always advisable to have a "pipe-cleaner" part. A small, not overly complex design that you can use to test the process and use to discover any bugs. It also helps if this is a lower volume part as there's always a risk of the new manufacturing process being unable to deliver high enough yields. Apple testing Samsung's 32nm process in the new Apple TV makes a lot of sense. There are far fewer Apple TVs sold than iPhones or iPads, so any troubles on the manufacturing side shouldn't really matter. Furthermore, Apple could also ship die-harvested (1 core disabled) 45nm A5s into Apple TVs if things get really bad.</p>
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Either way, it's clear that Apple is testing Samsung's 32nm process and this is likely the node we'll see debut in the next iPhone. As our own Brian Klug pointed out, this is the same part that's used in the new $399 version of the iPad 2 (iPad 2,4). Assuming Samsung's 32nm HK+MG process isn't horribly leaky at this point, we should actually see somewhat better battery life out of this new iPad 2 vs the older 45nm version.</p>
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<table align="center" border="0" cellpadding="0" cellspacing="1" width="575">
<tbody>
<tr class="tgrey">
<td align="center" colspan="9">
CPU Specification Comparison</td>
</tr>
<tr class="tlblue">
<td width="120">
CPU</td>
<td align="center" valign="middle" width="85">
Manufacturing Process</td>
<td align="center" valign="middle" width="85">
Cores</td>
<td align="center" valign="middle" width="85">
Transistor Count</td>
<td align="center" valign="middle" width="85">
Die Size</td>
</tr>
<tr>
<td class="tlgrey">
Apple A5X</td>
<td align="center" valign="middle">
45nm</td>
<td align="center" valign="middle">
2</td>
<td align="center" valign="middle">
?</td>
<td align="center" valign="middle">
163mm<sup>2</sup></td>
</tr>
<tr>
<td class="tlgrey">
Apple A5</td>
<td align="center" valign="middle">
45nm</td>
<td align="center" valign="middle">
2</td>
<td align="center" valign="middle">
?</td>
<td align="center" valign="middle">
122mm<sup>2</sup></td>
</tr>
<tr>
<td class="tlgrey">
Apple A5 (3rd gen Apple TV)</td>
<td align="center" valign="middle">
32nm</td>
<td align="center" valign="middle">
2</td>
<td align="center" valign="middle">
?</td>
<td align="center" valign="middle">
69.6mm<sup>2</sup></td>
</tr>
<tr>
<td class="tlgrey">
Intel Sandy Bridge 4C</td>
<td align="center" valign="middle">
32nm</td>
<td align="center" valign="middle">
4</td>
<td align="center" valign="middle">
995M</td>
<td align="center" valign="middle">
216mm<sup>2</sup></td>
</tr>
<tr>
<td class="tlgrey">
Intel Sandy Bridge 2C (GT1)</td>
<td align="center" valign="middle">
32nm</td>
<td align="center" valign="middle">
2</td>
<td align="center" valign="middle">
504M</td>
<td align="center" valign="middle">
131mm<sup>2</sup></td>
</tr>
<tr>
<td class="tlgrey">
Intel Sandy Bridge 2C (GT2)</td>
<td align="center" valign="middle">
32nm</td>
<td align="center" valign="middle">
2</td>
<td align="center" valign="middle">
624M</td>
<td align="center" valign="middle">
149mm<sup>2</sup></td>
</tr>
<tr>
<td class="tlgrey">
NVIDIA Tegra 3</td>
<td align="center" valign="middle">
40nm</td>
<td align="center" valign="middle">
4+1</td>
<td align="center" valign="middle">
?</td>
<td align="center" valign="middle">
~80mm<sup>2</sup></td>
</tr>
<tr>
<td class="tlgrey">
NVIDIA Tegra 2</td>
<td align="center" valign="middle">
40nm</td>
<td align="center" valign="middle">
2</td>
<td align="center" valign="middle">
?</td>
<td align="center" valign="middle">
49mm<sup>2</sup></td>
</tr>
</tbody>
</table>
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Source: AnandTech
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